View DS28E0212_4695765.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds28e02 combines 1024 bits of eeprom with challenge-and-response authentication security imple- mented with the fips 180-3 secure hash algorithm (sha-1). the 1024-bit eeprom array is configured as four pages of 256 bits with a 64-bit scratchpad to per- form write operations. all memory pages can be write protected, and one page can be put in eprom-emula- tion mode, where bits can only be changed from a 1 to a 0 state. each ds28e02 has its own guaranteed unique 64-bit rom registration number that is factory installed into the chip. the ds28e02 communicates over the single-contact 1-wire bus. the communica- tion follows the standard 1-wire protocol with the regis- tration number acting as the node address in the case of a multidevice 1-wire network. applications reference design license management system intellectual property protection sensor/accessory authentication and calibration medical consumable authentication printer cartridge configuration and monitoring features 1024 bits of eeprom memory partitioned into four pages of 256 bits on-chip 512-bit sha-1 engine to compute 160- bit message authentication codes (macs) and to generate secrets write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit mac as authorization user-programmable page write protection for page 0, page 3, or all four pages together user-programmable otp eprom emulation mode for page 1 (?rite to 0? communicates to host with a single digital signal at 12.5kbps or 35.7kbps using 1-wire protocol switchpoint hysteresis and filtering to optimize communication performance in the presence of noise reads and writes over 1.75v to 3.65v voltage range from -20? to +85? 6-lead tsoc and tdfn packages ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ________________________________________________________________ maxim integrated products 1 ordering information 219-0008; rev 1; 3/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. abridged data sheet part temp range pin-package ds28e02p+ -20 c to +85 c 6 tsoc ds28e02p+t&r -20 c to +85 c 6 tsoc ds28e02q+t&r -20 c to +85 c 6 tdfn-ep* (2.5k pcs) + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. io r pup v cc c gnd ds28e02 typical operating circuit 1-wire is a registered trademark of maxim integrated products, inc.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 2 _______________________________________________________________________________________ abridged data sheet absolute maximum ratings electrical characteristics (t a = -20? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. io voltage range to gnd .......................................-0.5v to +4v io sink current ...................................................................20ma operating temperature range ...........................-20? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (note 2) 1.75 3.65 v 1-wire pullup resistance r pup (notes 2, 3) 300 750 input capacitance c io (notes 4, 5) 1500 pf input load current i l io pin at v pup 0.05 5 a high-to-low switching threshold v tl (notes 5, 6, 7) 0.4 v pup C 0.89 v input low voltage v il (notes 2, 8) 0.30 v low-to-high switching threshold v th (notes 5, 6, 9) 0.74 v pup C 0.49 v switching hysteresis v hy (notes 5, 6, 10) 0.26 1.02 v output low voltage v ol at 4ma current load (note 11) 0.4 v standard speed, rpup = 750 20 recovery time (notes 2, 12) t rec overdrive speed 20 s standard speed 80 time slot duration (notes 2, 13) t slot overdrive speed 28 s io pin: 1-wire reset, presence-detect cycle standard speed 480 640 reset low time (note 2) t rstl overdrive speed 50 80 s standard speed 480 reset high time (note 14) t rsth overdrive speed 48 s standard speed 60 72 presence-detect sample time (notes 2, 15) t msp overdrive speed 7 10 s io pin: 1-wire write standard speed 60 120 write-zero low time (notes 2, 16) t w0l overdrive speed 8 15.5 s standard speed 1 15 write-one low time (notes 2, 16) t w1l overdrive speed 1 2 s io pin: 1-wire read standard speed 5 15 - read low time (notes 2, 17) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 2, 17) t msr overdrive speed t rl + 2 s eeprom io voltage < 3.65v 3.5 io voltage < 2.95v 2.5 programming current (notes 5, 18) i prog io voltage = 1.75v 1.0 ma
ds28e02 electrical characteristics (continued) (t a = -20? to +85?.) (note 1) parameter symbol conditions min typ max units programming time t prog (note 19) 25 ms at +25c 200,000 write/erase cycles (endurance) (notes 20, 21) n cy at +85c 50,000 data retention (notes 22, 23, 24) t dr at +85c 40 years sha-1 engine computation current i lcsha (notes 5, 18) ma computation time (notes 5, 25) t csha refer to full data sheet ms note 1: limits are 100% production tested at t a = +25? and/or t a = +85?. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recovery times. note 4: maximum value represents the internal parasite capacitance when v pup is first applied. once the parasite capacitance is charged, it does not affect normal communication. note 5: guaranteed by design, characterization, and/or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is a function of v pup , r pup , 1-wire timing, and capacitive loading on io. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic 0 is detected. note 8: the voltage on io must be less than or equal to v ilmax at all times the master is driving io to a logic 0 level. note 9: voltage above which, during a rising edge on io, a logic 1 is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io must drop by at least v hy to be detected as logic 0. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single device attached to a 1-wire line. note 13: defines maximum possible bit rate. equal to 1/(t w0lmin + t recmin ). note 14: an additional reset or communication sequence cannot begin until the reset high time has expired. note 15: interval after t rstl during which a bus master can read a logic 0 on io if there is a ds28e02 present. the power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up. note 16: in figure 12 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 17: in figure 12 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 18: current drawn from io during the eeprom programming interval or sha-1 computation. note 19: refer to full data sheet for this note. note 20: write-cycle endurance is degraded as t a increases. note 21: not 100% production tested; guaranteed by reliability monitor sampling. note 22: data retention is degraded as t a increases. note 23: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. note 24: eeprom writes can become nonfunctional after the data-retention time is exceeded. long-term storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125? or 40 years at +85?. note 25: refer to full data sheet for this note. 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation _______________________________________________________________________________________ 3 abridged data sheet
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 4 _______________________________________________________________________________________ abridged data sheet pin description pin tsoc tdfn-ep name function 1 3 gnd ground reference 2 2 io 1-wire bus interface. open-drain signal that requires an external pullup resistor. 3, 4, 5, 6 1, 4, 5, 6 n.c. not connected ep exposed pad (tdfn only). solder evenly to the boards ground plane for proper operation. refer to application note 3273: exposed pads: a brief introduction for additional information. detailed description the ds28e02 combines 1024 bits of eeprom orga- nized as four 256-bit pages, a 64-bit secret, a register page, a 512-bit sha-1 engine, and a 64-bit rom regis- tration number in a single chip. data is transferred seri- ally through the 1-wire protocol, which requires only a single data lead and a ground return. the ds28e02 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. data is first written to the scratchpad from where it can be read back. after the data has been verified, a copy scratch- pad command transfers the data to its final memory location, provided that the ds28e02 receives a match- ing 160-bit mac. the computation of the mac involves the secret and additional data stored in the ds28e02 including the device? registration number. the ds28e02 understands a unique command ?efresh scratchpad.?proper use of a refresh sequence after a copy scratchpad operation reduces the number of weak bit failures if the device is used in a touch envi- ronment (see the writing with verification section). the refresh sequence also provides a means to restore functionality in a device with bits in a weak state. in addition to its important use as a unique data value in cryptographic sha-1 computations, the device's 64-bit rom id guarantees unique identification and can be used to electronically identify the equipment in which it is used. the rom id is also used to address the device for the case of a multidrop 1-wire network environment, where multiple devices reside on a common 1-wire bus and operate independently of each other. applications of the ds28e02 include reference design license manage- ment, system intellectual property protection, accessory top view n.c. io gnd n.c. n.c. n.c. tsoc + 5 4 6 2 3 1 ds28e02 16 n.c. n.c. 25 io n.c. 34 gnd n.c. tdfn (3mm 3mm) top view ds28e02 2802 ymrrf + ep pin configurations
ds28e02 ds28e02 1-wire function control 1-wire net parasite power crc16 generator 64-bit rom 64-bit scratchpad 512-bit secure hash algorithm engine register page data memory 4 pages of 256 bits each memory and sha-1 function control unit figure 1. block diagram or consumable authentication and calibration, and printer cartridge configuration and monitoring. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds28e02. the ds28e02 has six main data compo- nents: 64-bit rom, 64-bit scratchpad, four 256-bit pages of eeprom, register page, and a 512-bit sha-1 engine. figure 2 shows the hierarchic structure of the 1-wire protocol. the bus master must first provide one of the seven rom function commands: read rom, match rom, search rom, skip rom, resume communication, overdrive-skip rom, or overdrive- match rom. upon completion of an overdrive-skip rom or overdrive-match rom command executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. the protocol required for these rom function commands is described in figure 10. after a rom function command is successfully executed, the mem- ory and sha-1 functions become accessible and the master can provide any one of the 9 available function commands. the function protocols are described in figure 8. all data is read and written least signifi- cant bit first. 64-bit rom each ds28e02 contains a unique rom registration num- ber that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits. see figure 3 for details. the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire crc is available in application note 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation _______________________________________________________________________________________ 5 abridged data sheet
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 6 _______________________________________________________________________________________ abridged data sheet available commands: data field affected: read rom match rom search rom skip rom resume overdrive-skip rom overdrive-match rom 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag 64-bit reg. #, rc-flag rc-flag rc-flag rc-flag, od-flag 64-bit reg.#, rc-flag, od-flag 1-wire rom function commands (see figure 10) refer to the full data sheet. device-specific memory function commands (see figure 8) command level: ds28e02 figure 2. hierarchic structure for 1-wire protocol msb 8-bit crc code 48-bit serial number msb msb lsb lsb lsb 8-bit family code msb lsb figure 3. 64-bit rom 27: understanding and using cyclic redundancy checks with maxim i button products . the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of the crc returns the shift register to all 0s. memory access the ds28e02 has four memory areas: data memory, secrets memory, register page with special function registers and user bytes, and a volatile scratchpad. the data memory is organized as four pages of 32 bytes. 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 4. 1-wire crc generator
ds28e02 figure 5. memory map 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation _______________________________________________________________________________________ 7 abridged data sheet refer to the full data sheet.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 8 _______________________________________________________________________________________ abridged data sheet figure 6. memory protection matrix address registers and transfer status the ds28e02 employs three address registers: ta1, ta2, and e/s (figure 7). these registers are common to many other 1-wire devices, but operate slightly differ- ently with the ds28e02. registers ta1 and ta2 must be loaded with the target address to which the data is writ- ten or from which data is read. register e/s is a read- only transfer-status register used to verify data integrity with write commands. since the scratchpad of the ds28e02 is designed to accept data in blocks of 8 bytes only, the lower 3 bits of ta1 are forced to 0 and bit # 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 (0) t1 (0) t0 (0) target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 1 pf 1 1 e2 (1) e1 (1) e0 (1) figure 7. address registers refer to the full data sheet.
ds28e02 the lower 3 bits of the e/s register (ending offset) always read 1. this indicates that all the data in the scratchpad is used for a subsequent copying into main memory or secret. bit 5 of the e/s register, called pf or partial byte flag, is a logic 1 if the number of data bits sent by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of power. a valid write to the scratchpad clears the pf bit. bits 3, 4, and 6 have no function; they always read 1. the partial flag supports the master checking the data integrity after a write command. the highest valued bit of the e/s reg- ister, called authorization accepted (aa), acts as a flag to indicate that the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. writing with verification to write data to the ds28e02, the scratchpad must be used as intermediate storage. first, the master issues the write scratchpad command, which specifies the desired target address and the data to be written to the scratchpad. note that writes to data memory must be performed on 8-byte boundaries with the three lsbs of the target address t[2:0] equal to 000b. therefore, if t[2:0] are sent with nonzero values, the device sets these bits to 0 and uses the modified address as the target address. the master should always send eight complete data bytes. after the 8 bytes of data have been transmitted, the master can elect to receive an inverted crc-16 of the write scratchpad command, the address as sent by the master, and the data as sent by the master. the master can compare the crc to the value it has calculated itself to determine if the commu- nication was successful. after the scratchpad has been written, the master should always perform a read scratchpad to verify that the intended data was in fact written. during a read scratchpad, the ds28e02 repeats the target address ta1 and ta2 and sends the contents of the e/s register. the partial flag (bit 5 of the e/s register) is set to 1 if the last data byte the ds28e02 received during a write scratchpad or refresh scratch- pad command was incomplete, or if there was a loss of power since data was last written to the scratchpad. the authorization-accepted (aa) flag (bit 7 of the e/s register) is normally cleared by a write scratchpad or refresh scratchpad; therefore, if it is set to 1, it indicates that the ds28e02 did not understand the proceeding write (or refresh) scratchpad command. in either of these cases, the master should rewrite the scratchpad. after the master receives the e/s register, the scratch- pad data is received. the descriptions of write scratch- pad and refresh scratchpad provide clarification of what changes can occur to the scratchpad data under certain conditions. an inverted crc of the read scratchpad command, target address, e/s register, and scratchpad data follows the scratchpad data. as with the write scratchpad command, this crc can be com- pared to the value the master has calculated to deter- mine if the communication was successful. after the master has verified the data, it can send the copy scratchpad to copy the scratchpad to memory. 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation _______________________________________________________________________________________ 9 abridged data sheet refer to the full data sheet.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 10 ______________________________________________________________________________________ abridged data sheet memory and sha-1 function commands this section describes the commands and flowcharts needed to use the memory and sha-1 engine of the device. refer to the full data sheet for more information.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 22 ______________________________________________________________________________________ abridged data sheet 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds28e02 is a slave device. the bus master is typically a microcon- troller. the discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transac- tions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master.
ds28e02 hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the ds28e02 is open drain with an internal circuit equivalent to that shown in figure 9. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the ds28e02 supports both a stan- dard and overdrive communication speed of 12.5kbps (max) and 35.7kbps (max), respectively. note that lega- cy 1-wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. the value of the pullup resistor primarily depends on the network size and load conditions. the ds28e02 requires a pullup resistor of 750 ? (max) at any speed. the idle state for the 1-wire bus is high. if for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16? (overdrive speed) or more than 120? (standard speed), one or more devices on the bus could be reset. transaction sequence the protocol for accessing the ds28e02 through the 1-wire port is as follows: initialization rom function command memory/sha function command transaction/data rx r pup i l v pup bus master open-drain port pin 100 ? mosfet tx rx tx data ds28e02 1-wire port rx = receive tx = transmit figure 9. hardware configuration 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ______________________________________________________________________________________ 23 abridged data sheet
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 24 ______________________________________________________________________________________ abridged data sheet initialization all transactions on the 1-wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds28e02 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. 1-wire rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands that the ds28e02 supports. all rom function commands are 8 bits long. a list of these commands follows (see the flowchart in figure 10). read rom [33h] the read rom command allows the bus master to read the ds28e02? 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data col- lision occurs when all slaves try to transmit at the same time (open drain produces a wired-and result). the resultant family code and 48-bit serial number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit device registration number, allows the bus master to address a specific ds28e02 on a multidrop bus. only the ds28e02 that exactly matches the 64-bit registration number responds to the subsequent memory or sha-1 function command. all other slaves wait for a reset pulse. this command can be used with a single device or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the regis- tration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the sec- ond slot, each slave device participating in the search outputs the complemented value of its registration num- ber bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participat- ing in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the search tree. after one complete pass, the bus master knows the registration number of a single device. additional passes identify the registra- tion numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. skip rom [cch] this command can save time in a single-drop bus sys- tem by allowing the bus master to access the memory functions without providing the 64-bit registration num- ber. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result).
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ______________________________________________________________________________________ 25 abridged data sheet ds28e02 tx presence pulse bus master tx reset pulse bus master tx rom function command ds28e02 tx crc byte ds28e02 tx family code (1 byte) ds28e02 tx serial number, user-defined field, and custom id (6 bytes) rc = 0 master tx bit 0 rc = 0 rc = 0 rc = 0 od = 0 y y y y y y y y 33h read rom command? n 55h match rom command? bit 0 match? bit 0 match? n n n n n n n f0h search rom command? od reset pulse? n n cch skip rom command? n rc = 1 master tx bit 1 master tx bit 63 bit 1 match? bit 63 match? y y rc = 1 from memory and sha-1 function flowchart (figure 8) to memory and sha-1 function flowchart (figure 8) ds28e02 tx bit 0 ds28e02 tx bit 0 master tx bit 0 bit 1 match? bit 63 match? ds28e02 tx bit 1 ds28e02 tx bit 1 master tx bit 1 ds28e02 tx bit 63 ds28e02 tx bit 63 master tx bit 63 y to figure 10b to figure 10b from figure 10b from figure 10b figure 10a. rom functions flowchart
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 26 ______________________________________________________________________________________ abridged data sheet master tx bit 0 rc = 0; od = 1 rc = 0; od = 1 od = 0 (see note) note: the od flag remains at 1 if the device was already at overdrive speed before the overdrive-match rom command was issued. (see note) (see note) rc = 1? y y a5h resume command? n y 3ch overdrive- skip rom? n y 69h overdrive- match rom? n n od = 0 n od = 0 n master tx bit 1 master tx bit 63 y y rc = 1 y bit 0 match? master tx reset? bit 63 match? bit 1 match? n y n y master tx reset? n to figure 10a from figure 10a from figure 10a to figure 10a figure 10b. rom functions flowchart
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ______________________________________________________________________________________ 27 abridged data sheet resistor master ds28e02 t rstl t rsth master tx "reset pulse" master rx "presence pulse" v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp figure 11. initialization procedure: reset and presence pulse resume [a5h] to maximize the data throughput in a multidrop environ- ment, the resume command is available. this command checks the status of the rc bit and, if it is set, directly transfers control to the memory and sha-1 function com- mands, similar to a skip rom command. the only way to set the rc bit is through successfully executing the match rom, search rom, or overdrive-match rom command. once the rc bit is set, the device can repeat- edly be accessed through the resume command. accessing another device on the bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command. overdrive-skip rom [3ch] on a single-drop bus this command can save time by allowing the bus master to access the memory func- tions without providing the 64-bit registration number. unlike the normal skip rom command, the overdrive- skip rom command sets the ds28e02 into the over- drive mode (od = 1). all communication following this command must occur at overdrive speed until a reset pulse of minimum 480? duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a match rom or search rom com- mand sequence. this speeds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive-skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- and result). overdrive-match rom [69h] the overdrive-match rom command followed by a 64- bit registration number transmitted at overdrive speed allows the bus master to address a specific ds28e02 on a multidrop bus and to simultaneously set it in overdrive mode. only the ds28e02 that exactly matches the 64- bit number responds to the subsequent memory or sha-1 function command. slaves already in overdrive mode from a previous overdrive-skip rom or success- ful overdrive-match rom command remain in overdrive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480? dura- tion. the overdrive-match rom command can be used with a single device or multiple devices on the bus. 1-wire signaling the ds28e02 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and pres- ence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the ds28e02 can communicate at at two differ- ent speeds: standard speed and overdrive speed. if not explicitly set into the overdrive mode, the ds28e02 communicates at standard speed. while in overdrive mode, the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 11 as , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds28e02 when determining a logical level, not triggering any events.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 28 ______________________________________________________________________________________ abridged data sheet figure 11 shows the initialization sequence required to begin any communication with the ds28e02. a reset pulse followed by a presence pulse indicates that the ds28e02 is ready to receive data, given the correct rom and memory and sha-1 function command. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480 s or longer exits the overdrive mode, returning the device to standard speed. if the ds28e02 is in overdrive mode and t rstl is no longer than 80 s, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80 s and 480 s, the device resets, but the communication speed is undetermined. after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor. when the threshold v th is crossed, the ds28e02 waits and then transmits a pres- ence pulse by pulling the line low. to detect a pres- ence pulse, the master must test the logical state of the 1-wire line at t msp . read/write time slots data communication with the ds28e02 takes place in time slots that carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 12 illus- trates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below the threshold v tl , the ds28e02 starts its internal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write- one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the volt- age on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds28e02 needs a recovery time t rec before it is ready for the next time slot. slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds28e02 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds28e02 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the ds28e02 on the other side define the master sampling window (t msrmin to t msrmax ), in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds28e02 to get ready for the next time slot. note that t rec specified herein applies only to a single ds28e02 attached to a 1-wire line. for multide- vice configurations, t rec must be extended to accom- modate the additional 1-wire device input capacitance. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible only during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are suscep- tible to noise of various origins. depending on the phys- ical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur- ing the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command com- ing to a dead end or cause a device-specific function command to abort. for better performance in network applications, the ds28e02 uses a new 1-wire front-end, which makes it less sensitive to noise. the ds28e02? 1-wire front-end differs from traditional slave devices in two characteristics. 1) there is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high-frequency noise. this additional filtering does not apply at over- drive speed. 2) there is a hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it is not recognized (figure 13). the hysteresis is effective at any 1-wire speed.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ______________________________________________________________________________________ 29 abridged data sheet resistor master resistor master resistor master ds28e02 v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slot write-zero time slot read-data time slot figure 12. read/write timing diagrams
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation 30 ______________________________________________________________________________________ abridged data sheet crc generation the ds28e02 uses two different types of crcs. one crc is an 8-bit type that is computed at the factory and is stored in the most significant byte of the 64-bit regis- tration number. the bus master can compute a crc value from the first 56 bits of the 64-bit registration num- ber and compare it to the value read from the ds28e02 to determine if the registration number has been received error-free. the equivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (noninverted) form. the other crc is a 16-bit type, which is used for error detection with memory and sha-1 commands. for details, refer to the full data sheet. v pup v th v hy 0v figure 13. noise suppression scheme
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation ______________________________________________________________________________________ 33 abridged data sheet package type package code outline no. land pattern no. 6 tsoc d6+1 21-0382 90-0321 6 tdfn-ep t633+2 21-0137 90-0058 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
ds28e02 1-wire sha-1 authenticated 1kb eeprom with 1.8v operation abridged data sheet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 34 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/10 initial release 1 3/12 revised the electrical characteristics table notes 1, 4, 15; added the land pattern numbers to the package information table 3, 33

▲Up To Search▲

Price & Availability of DS28E0212

	To Download DS28E0212 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .